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Multiple Instruction Stream Microprocessor Organization

IP.com Disclosure Number: IPCOM000076355D
Original Publication Date: 1972-Feb-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Duggan, PN: AUTHOR

Abstract

The described organization increases the logical decision rate of a microprocessor. An instruction pipelining technique provides for execution of microinstructions simultaneously from control storages of four logical microprocessors, over buses 0, 1, 2, 3. The microinstructions are tagged according to stream and migrate through four platforms for phases A, B, C, D. Each platform contains those decodes and controls necessary during that particular phase of execution. High-speed logical storage 5 and 7 are provided for holding and manipulating parameters. In addition, each microprocessor may communicate with external facilities via buses 9 and 11. The organization also provides for the addressing of a predetermined amount of high-speed local storage useful for operand manipulation.

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Multiple Instruction Stream Microprocessor Organization

The described organization increases the logical decision rate of a microprocessor. An instruction pipelining technique provides for execution of microinstructions simultaneously from control storages of four logical microprocessors, over buses 0, 1, 2, 3. The microinstructions are tagged according to stream and migrate through four platforms for phases A, B, C, D. Each platform contains those decodes and controls necessary during that particular phase of execution. High-speed logical storage 5 and 7 are provided for holding and manipulating parameters. In addition, each microprocessor may communicate with external facilities via buses 9 and 11. The organization also provides for the addressing of a predetermined amount of high-speed local storage useful for operand manipulation.

Microinstruction execution is divided into four phases, with each logical microprocessor having a microinstruction in a phase at any one time. Phase A generates the next microinstruction in a phase at any one time. Phase A generates the next microinstruction address and moves local store and external facility addresses to their read address registers. Phase B initiates the fetch of the next microinstruction, reads out the local store and external facility and moves addresses along the pipeline. Phase C combines the local store and external facility operands in the ALU 13 and places the result in an output register, while setting sta...