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Browse Prior Art Database

Via Etching Process

IP.com Disclosure Number: IPCOM000076375D
Original Publication Date: 1972-Feb-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Drotar, JS: AUTHOR [+2]

Abstract

Electroplating cannot be controlled sufficiently to form vias having the same dimensional length in printed-circuit boards. Therefore, additional processing is usually required to bring the vias to uniform dimensional requirements.

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Via Etching Process

Electroplating cannot be controlled sufficiently to form vias having the same dimensional length in printed-circuit boards. Therefore, additional processing is usually required to bring the vias to uniform dimensional requirements.

This is a method of controlled chemical etch of over-plated vias to achieve uniform dimensions. An etching solution such as ferric chloride for vias formed of copper is absorbed in a "blotter" material. The blotter is filled with an etchant solution and wiped across the via pattern. A repetitive cycle of wiping with the blotter and spray rinsing with deionized water rapidly removes high spots while leaving the recessed areas untouched. The etching solution is confined to the blotter and is not free to flow into the crevices and recesses. The resolution of the method is dependent upon a judicious choice of blotter material and etchant.

Alternatively, the etching process can also be used to make raised studs to accommodate direct chip attachment to a printed-circuit board. Here, a thick-film photoresist, such as RISTON*, would be applied to the printed-circuit board with a thickness corresponding to the desired stud dimension. After plating and leveling the studs, the photoresist is stripped and the studs remain free-standing for a direct chip attachment. * Trademark of E. I. du Pont de Nemours & Co.

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