Browse Prior Art Database

Exclusive OR Set Latch

IP.com Disclosure Number: IPCOM000076409D
Original Publication Date: 1972-Feb-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Hannaford, CW: AUTHOR

Abstract

In the prior art exclusive OR set latch circuit 1 of Fig. 1, comprising true-complement generators 2 and 3, satisfies one of the conduction requirements of AND gate 4 when inputs A and B are dissimilar. Upon the concurrence of a read signal on input 5, AND circuit 4 provides an output on line 6 which is fed back to latching AND circuit 7 to maintain the output (until a reset is applied to line 8) independent of subsequent input conditions at A and B.

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Exclusive OR Set Latch

In the prior art exclusive OR set latch circuit 1 of Fig. 1, comprising true- complement generators 2 and 3, satisfies one of the conduction requirements of AND gate 4 when inputs A and B are dissimilar. Upon the concurrence of a read signal on input 5, AND circuit 4 provides an output on line 6 which is fed back to latching AND circuit 7 to maintain the output (until a reset is applied to line 8) independent of subsequent input conditions at A and B.

One increment of logic delay inherent in the circuit of Fig. 1 is eliminated with a concomitant reduction in power by utilizing exclusive OR circuit 9 of Fig. 2 as the setting gate of the latch, and applying the read control signal directly thereto via line 10. As shown in more detail in Fig. 3, if inputs at A and B are both binary 1 and a negative read signal is applied to the base of transistor 12, current from current source I(1) flows through transistor 11. Similarly, current flows through transistor 13 when the inputs at A and B are both binary 0. However, current flows through transistors 14 and 15 and through resistor R when the inputs at A and B are 0,1 and 1,0, respectively. The current through resistor R turns on transistor 16 and produces an output on line 17.

The output on line 17 is fed back to turn off transistor 18, which causes the current I(2) to flow through transistor 19 in the absence of a reset signal on line
21. The current flowing through transistor 19 also flows through...