Browse Prior Art Database

Distributed Inverter

IP.com Disclosure Number: IPCOM000076411D
Original Publication Date: 1972-Feb-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 21K

Publishing Venue

IBM

Related People

Kemerer, DW: AUTHOR

Abstract

Additional devices, resistor R2 and field-effect transistor (FET) T2, are added to a conventional inverter, resistor R1 and FET T1, in order to reduce the fall time and downlevel at the new output 22. Input 20 is applied to the gates of T1 and T2.

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Distributed Inverter

Additional devices, resistor R2 and field-effect transistor (FET) T2, are added to a conventional inverter, resistor R1 and FET T1, in order to reduce the fall time and downlevel at the new output 22. Input 20 is applied to the gates of T1 and T2.

In a conventional inverter, T1 must be large in order to guarantee a fast fall time and low downlevel at output 21. In this circuit, T1 is considerably smaller since R2 and T2 improve the fall time and downlevel at 22. Output 21 is used where downlevel is not critical.

Operation is shown for N channel FET's and resistive loads. P channel FET's and FET loads may also be used.

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