Browse Prior Art Database

Chip on Card

IP.com Disclosure Number: IPCOM000076436D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Dorler, J: AUTHOR [+2]

Abstract

The present techniques allow monolithic chips to be directly mounted on cards. First, a suitable metallic voltage plane 10 is selected, Fig. 1. Next, a plurality of standoff metal elements, such as copper washers 12, are selectively disposed and bonded to the voltage plane 10, Fig. 2. Then, a plurality of semiconductor chips 14 are bonded to the plurality of washers 12 in any suitable manner, such as by solder reflow, Fig. 3. Next X and Y conductive planes depicted at 16 and 18, respectively, are disposed on the voltage plane 10, Fig. 4. One manner of fixing the X and Y planes is to employ thin insulated adhesive epoxy layers 20 and 22. The plurality of chips 14 are mounted in the step shown in Fig. 3. However, the semiconductor chips can also be mounted subsequent to the step shown in Fig.

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Chip on Card

The present techniques allow monolithic chips to be directly mounted on cards. First, a suitable metallic voltage plane 10 is selected, Fig. 1. Next, a plurality of standoff metal elements, such as copper washers 12, are selectively disposed and bonded to the voltage plane 10, Fig. 2. Then, a plurality of semiconductor chips 14 are bonded to the plurality of washers 12 in any suitable manner, such as by solder reflow, Fig. 3. Next X and Y conductive planes depicted at 16 and 18, respectively, are disposed on the voltage plane 10, Fig. 4. One manner of fixing the X and Y planes is to employ thin insulated adhesive epoxy layers 20 and 22. The plurality of chips 14 are mounted in the step shown in Fig. 3. However, the semiconductor chips can also be mounted subsequent to the step shown in Fig. 4, in accordance with yield considerations. Finally, a plurality of thermocompression wire bonds 24 are employed to selectively connect the semiconductor chips 12 to the desired X and Y planes, and then the devices are encapsulated by a plurality of means 28 according to any well known number of encapsulation techniques, such as plastics, cans, etc. as shown in Fig. 5.

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