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Nonsymmetrical Memory Cell

IP.com Disclosure Number: IPCOM000076450D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Platt, S: AUTHOR

Abstract

This bipolar memory cell provides single-ended sensing while relaxing the requirement for base-emitter voltage tracking for cells common to a word line (row). Three signal lines are required to select, read, and write this cell.

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Nonsymmetrical Memory Cell

This bipolar memory cell provides single-ended sensing while relaxing the requirement for base-emitter voltage tracking for cells common to a word line (row). Three signal lines are required to select, read, and write this cell.

In standby, cell current conducts through the inside emitter A of the on side. The inside emitters of cells common to a word line (row) are not connected. Resistor R2 is integrated in every cell. To perform a read, the bit-read line is lowered and the word line raised. A "1" state cell (transistor T2 on, transistor T1 off) conducts sense current through the outside emitter B of transistor T2 into the bit sense line. A "0" state (transistor T1 on, transistor T2 off) conducts no current into the bit-sense line. The write operation is performed by lowering either the bit write 0 or the bit write 1 line.

The presence of diode D1 as the collector load for transistor T2 permits a large sense signal to conduct during a read 1 operation. The integration of resistor R2 into every cell and the absence of inside emitter connection between cells, eliminates the current robbing, due to base-emitter voltage mismatch, of cells common to a word line (row).

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