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Dynamically Controlling the Testing of Stored Information in a Monolithic Memory

IP.com Disclosure Number: IPCOM000076454D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 4 page(s) / 102K

Publishing Venue

IBM

Related People

Pulyer, RC: AUTHOR [+2]

Abstract

In computer controlled testing shown in Fig. 1, the tester under the control of the control processing unit (CPU) will conventionally apply the addresses of the storage locations to the memory which, in the illustrated example, is a 1024-bit read-only memory, and will sense the resulting output at each storage location. In addition, the tester will determine the powering of the read-only memory through the module select, V(EE), V(REF), and V(CC) inputs shown. In the test system illustrated, a combination of voltage levels (indicative of either a "1" or a "0" on the eight address inputs to the monolithic memory will indicate which of 256 storage locations is being addressed, and each of said 256 storage locations will have four stored bits which will produce an output shown at output points 1-4.

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Dynamically Controlling the Testing of Stored Information in a Monolithic Memory

In computer controlled testing shown in Fig. 1, the tester under the control of the control processing unit (CPU) will conventionally apply the addresses of the storage locations to the memory which, in the illustrated example, is a 1024-bit read-only memory, and will sense the resulting output at each storage location.

In addition, the tester will determine the powering of the read-only memory through the module select, V(EE), V(REF), and V(CC) inputs shown. In the test system illustrated, a combination of voltage levels (indicative of either a "1" or a "0" on the eight address inputs to the monolithic memory will indicate which of 256 storage locations is being addressed, and each of said 256 storage locations will have four stored bits which will produce an output shown at output points 1-4. Since the tester must sense a total of 1024 outputs for each monolithic memory chip, it is critical that testing be conducted as rapidly as possible. In order to insure that the tests be carried out as rapidly as possible, it had been the practice to store in the CPU, such as an IBM 1800 computer, every single instruction to the tester in order to cause the tester to put forth the voltage levels necessary to address each of the 256 storage locations, as well as to apply the appropriate powering levels, and to read the resulting 1024 outputs. Where there are a large number of outputs to be read, as in the present case, the storage core requirements for storing the instructions to the tester in the CPU becomes completely excessive.

The present program provides a system which will permit the CPU to dynamically set up the instructions to the tester in chronological sequence, based upon information stored in a series of tables in the CPU which occupy core storage space some orders of magnitude smaller than that which would be required to store all of the instructions. Because the tester is capable of carrying out the instruction for reading a given one of the 1024 bits at a considerably higher rate than the CPU is capable of setting up the next series of instructions for the next bit to be read, the present program involves an approach wherein the instructions to the tester for determining the next succeeding bit are being set up simultaneously with the reading of the preceding bit by the tester. In order to accomplish this result, the present program utilized two identical sets of tables shown as Group A tables and Group B tables as well as a miscellaneous set of tables, as shown in Fig. 4.

With reference first to Figs. 2A and 1, consider how the program operates. The tester is initiated by the CPU by applying a set of instructions found in Table INST, Fig. 4. These instructions cause the tester to apply power to the chip under test through lines module select, V(EE),V(REF) and V(CC), as well as voltage levels to the eight address lines. Next, block 10, the first o...