Browse Prior Art Database

Stacked High Density Multichip Module

IP.com Disclosure Number: IPCOM000076457D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Jarvela, RA: AUTHOR [+3]

Abstract

This is a stacked high-density multichip module providing extremely dense memory chip packaging for large-capacity storage applications.

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Stacked High Density Multichip Module

This is a stacked high-density multichip module providing extremely dense memory chip packaging for large-capacity storage applications.

A substrate 1 is provided with pins in a conventional manner. A staggered configuration with 25 pins is shown. Chip carrier substrates 3 and 4 are used to mount chips 5 with flip-chip solder reflow joints. Peripheral to each chip carrier are located 48 holes in accordance with the present example. Both chip carriers 3 and 4 are personalized with wiring. The holes on each chip carriers are plated through and provide vias from the chip mounting side to communicate with either the interposer 6, as is the case with chip carrier 4, or the lower pin substrate 1 as is the case with chip carrier 3. The substrate interposer 6 is simply several metal punchings molded into a heat-resistant holder, which engage the vias of the chip carriers 3 and 4 and provide an electrical path by solder joints. The package is conventionally capped using an aluminum can 7. Any number of chip carriers 3 and 4 can be stacked using additional interposers 6. It is also possible to replace the plated through holes in the periphery of the chip carriers with plated notches along the edges. Savings in cost and improved packaging density are obtained by this technique.

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