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Double Diffused MOS Device and Process of Fabricating

IP.com Disclosure Number: IPCOM000076460D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Barson, F: AUTHOR

Abstract

This field-effect transistor is produced by sequentially diffusing two impurities through a single opening, such that the impurities travel laterally between two impervious dielectric layers.

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Double Diffused MOS Device and Process of Fabricating

This field-effect transistor is produced by sequentially diffusing two impurities through a single opening, such that the impurities travel laterally between two impervious dielectric layers.

In the process, a dielectric layer 10 is formed on a suitable substrate 12 as for example, silicon. A layer 14 of semiconductor material is then deposited. Layer 14 can be either polycrystalline or monocrystalline. When semiconductor material is deposited on sapphire, utilizing the proper conditions, a monocrystalline layer can be produced. Subsequently, a layer 16 is formed on the surface of layer 14 and openings 17 made therein for introducing an impurity to form isolation region 18. Region 18 is ordinarily rectangular or annular in shape to isolate the enclosed region of layer 14. When layer 14 is doped with an N- type dopant the diffused regions 18 is doped with a P type impurity. Opening 17 is then reoxidized and a central opening 19 made by conventional photolithographic techniques. A first diffusion with a P type impurity forms diffused region 20 and a second N+ type impurity results in diffused region 22. Opening 19 is then covered by reoxidation and a second annular opening made over the P type diffused region 20, which is subsequently reoxidized forming thin oxide 24, as shown in Fig. 3. Openings are made through layer 16, a layer of metallurgy deposited, and the layer subsequently etched to obtained the desired...