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Two Phase Dynamic Shift Register

IP.com Disclosure Number: IPCOM000076478D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Fischer, HP: AUTHOR [+2]

Abstract

Applying a data voltage to the middle of a NAND circuit and clock signals to the ends of the NAND circuit in a dynamic shift register, increases clock rate and reduces capacitive loading on phase-driver circuits.

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Two Phase Dynamic Shift Register

Applying a data voltage to the middle of a NAND circuit and clock signals to the ends of the NAND circuit in a dynamic shift register, increases clock rate and reduces capacitive loading on phase-driver circuits.

A portion of a dynamic shift register is shown in Fig. 1. Each stage comprises two NAND circuits (FET's 1, 3, 4 and 5, 7, 8) and two charge transfer gates (FET's 2 and 6). A data input is provided to the middle FET's 3 and 7 of each NAND circuit. Phase 1 and phase 2 clock pulses are provided to the end devices 1, 4 and 5, 8 of each NAND circuit. The application of both clock pulses to each NAND circuit eliminates "dead" time between the phase 1 and phase 2 clock signals in a usual or standard six device storage cell. The output from each NAND circuit is Provided to a charge transfer circuit including capacitors C2 and C4. VDD may be replaced by phase 1 at FET 1 and by phase 2 at FET 5, if desired.

Input data is transferred to C2 at phase 1, as shown in Fig. 2. Also at phase 1, C3 is precharged through 1. At phase 2, C3 and C4 will be discharged if a "one" had been transferred to C2 during the previous phase 1. Otherwise, charge will be transferred to C4 during phase 2. C5 is also precharged through FET 5 at phase 2 and this node is evaluated during the next phase 1 pulse. Output signals are provided as noted in Fig. 2.

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