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High Speed Floating Point Accumulator

IP.com Disclosure Number: IPCOM000076481D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Sproul, W: AUTHOR

Abstract

The accumulation of sums of products, as in Epsilon(i). (a.(i) x b.(i)) may be accomplished by gating the product of the multiplication directly into an accumulating adder. Further time and hardware is conserved if the multiplication is not completed, but rather the product is in unassimulated sum and carry form as would be generated from the final carry-save adder (CSA) of the multiplier. In this form there are two bits for every bit position of the product and the product must be assimilated in a carry-propagate adder (CPA). This same CPA may be used to add in the accumulator to the product forming the new accumulated product. Fig. 1 shows a simplified diagram of this process.

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High Speed Floating Point Accumulator

The accumulation of sums of products, as in Epsilon(i).
(a.(i) x b.(i)) may be accomplished by gating the product of the multiplication directly into an accumulating adder. Further time and hardware is conserved if the multiplication is not completed, but rather the product is in unassimulated sum and carry form as would be generated from the final carry-save adder (CSA) of the multiplier.

In this form there are two bits for every bit position of the product and the product must be assimilated in a carry-propagate adder (CPA). This same CPA may be used to add in the accumulator to the product forming the new accumulated product. Fig. 1 shows a simplified diagram of this process.

Floating-point addition is somewhat complicated in that the operands must be relatively shifted by an amount equal to the exponent difference.

Floating-point accumulation is even further complicated by the accumulated sum being unnormalized and requiring a data dependent post-normalization shift, with corresponding exponent update prior to accumulating the next product. These two complexities are resolved by the device of Fig. 2, while at the same time greatly reducing the hardware requirements and speeding up the operation relative to what would be considered a straightforward approach. The device of Fig. 2 uses a single shifter. Only the accumulator is preshifted and it is preshifted either left or right in a wrap-around preshifter, such that its final alignment relative to the product is as specified by the exponent difference.

To demonstrate the operation of the preshift, two examples will be given. If the product exponent is larger than the accumulator exponent, them the accumulator fraction must be right shifted to a number of digits equal to the exponent difference. This is accomplished by right shifting the accumulator and inhibiting any wrap-around shift, so that the leading high-order digits where data was shifted out will be zero. If the accumulator exponent is larger than the product exponent, then, instead of right shifting the product, the accumulator will be left shifted. This is accomplished by left shifting the accumulator the required number of digits and allowing the high order digits to be wrap-around shifted. The product low-order digits that would normally have been shifted out must be blocked out of the adder and not allowed to participate in the accumulation. This is accomplished using selective blocking ingating to the adder. Now there are two prealigned operands to be added where the high-order digit is not at the normal high-order end of the adder, but somewhere in the middle. Actually, this poses no problem other than some bookkeeping to remember where the high-order digit of the sum will be located. The adder may be considered to be a wrap- around adder with carry propagation capability all the way around. This is the way a normal adder is built. However, in order to prevent an overflow car...