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N Way Testpoint for Complex LSI Design

IP.com Disclosure Number: IPCOM000076482D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Savkar, AD: AUTHOR

Abstract

A plurality of points within the circuitry on a large-scale integrated (LSI) chip may be monitored through a single output pad or may be controlled through a single input pad by the provision of an N-stage recirculating shift register located on the same chip, to sequentially address the N points to be tested or controlled.

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N Way Testpoint for Complex LSI Design

A plurality of points within the circuitry on a large-scale integrated (LSI) chip may be monitored through a single output pad or may be controlled through a single input pad by the provision of an N-stage recirculating shift register located on the same chip, to sequentially address the N points to be tested or controlled.

In the N-way testpoint configuration of Fig. 1, the N-stage recirculating shift register is supplied with address bits through the address bit input pad, which are cycled through cells 1 to N by shift pulses supplied through the clock pad. The output of each of the N cells of the shift register is connected to one of N AND gates A1 to AN. The other input to each of the respective AND gates is connected to the test point TP1 to TPN within the main circuits on the LSI chip. The output of each respective AND gate is passed through the NOR gate and out to the N-Way testpoint pad. The shift register is initialized to an all zero configuration When the given testpoint TPi is to be monitored (1 < i < N), a one bit followed by i-1 zero bits is shifted into the cell of the recirculating shift register, corresponding to the ith test Point to be monitored. The one bit in the ith cell of the shift register conditions the ith AND gate and the point TPi to be monitored is connected by the NOR gate to the N-Way testpoint pad. All other AND gates are disabled, since the remaining N-1 cells of the shift register have a zero therein. When a second testpoint TIj is to be monitored (j does not = i), the one bit in the ith cell is shifted into the jth cell corresponding to the new testpoint. All N testpoints may be periodically monitored by cycling the one bit through the N stage recirculating shift register by a periodic clock pulse applied to the clock pad. An example of points TPi to be monitored are the intermediate points of a large counter or the intermediate points of a multistage frequency divider.

In the N-way control point configuration of Fig. 2, the Nistage recirculating shift register is supplied with address bits through the address bit input pad, which are cycled through cells 1 to N by shift pulses supplied through the pad. The output of each of the N cells of the shift register is connected to one of the N AND gates A1 to AN. The other input to each of the respective AND gates is...