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Random Key Generator for Ciphering System

IP.com Disclosure Number: IPCOM000076505D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Skatrud, RO: AUTHOR

Abstract

It has been proposed to encode or decode information by Exclusive ORing data with a sequence of characters derived from Exclusive ORed combinations of memory sequences, including permutations of the combinations of sequences. The randomness of the sequence of characters is improved by using alternate ones of the character sequence to select the memory sequences to be combined. As indicated in the figure, a storage area 1, originally loaded with a known random-bit sequence, is divided into a plurality of partitions 2, 3, etc. The address of the character to be read out of each storage partition 2, 3, etc. is held in an individual address counter 5, 6, etc. The address counters 5, 6, etc.

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Random Key Generator for Ciphering System

It has been proposed to encode or decode information by Exclusive ORing data with a sequence of characters derived from Exclusive ORed combinations of memory sequences, including permutations of the combinations of sequences. The randomness of the sequence of characters is improved by using alternate ones of the character sequence to select the memory sequences to be combined. As indicated in the figure, a storage area 1, originally loaded with a known random-bit sequence, is divided into a plurality of partitions 2, 3, etc. The address of the character to be read out of each storage partition 2, 3, etc. is held in an individual address counter 5, 6, etc. The address counters 5, 6, etc. will normally be incremented for each character, but can be loaded with different initial numbers for changing the permutations of addresses. The characters read out of storage 1 are selectively passed through gates 7 into buffers 8. All of the gates 7 for a storage partition 2, 3, etc. are opened and closed by a 1 or a 0 bit stored in a control register 9, which has one bit position for each storage partition. The characters stored in buffers 8 are Exclusive OR (XOR) by the levels of Exclusive OR circuits 10 into a final XOR 11. The character present in XOR 11 is alternately gated to control register 9 to control the gates 7 to pass or not pass the next read out characters, or is gated to a key buffer 12 as the key character to be combine...