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Reversible On Chip Redundancy Scheme

IP.com Disclosure Number: IPCOM000076508D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Chin, W: AUTHOR [+2]

Abstract

In monolithic-memory circuitry wherein the memory array comprises a plurality of storage cells on a monolithic chip, it has been recognized that extra word and bit lines should be provided on the chip to replace bad word and bit lines by appropriate decode and address circuitry. The circuitry for achieving such redundancy is described in IBM Technical Disclosure Bulletin, Volume 14, No. 5, October 1971. pp. 1513 and 1514. The circuitry in this referenced article appears to permanently replace the bad word or bit line with one of the redundant lines.

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Reversible On Chip Redundancy Scheme

In monolithic-memory circuitry wherein the memory array comprises a plurality of storage cells on a monolithic chip, it has been recognized that extra word and bit lines should be provided on the chip to replace bad word and bit lines by appropriate decode and address circuitry. The circuitry for achieving such redundancy is described in IBM Technical Disclosure Bulletin, Volume 14, No. 5, October 1971. pp. 1513 and 1514. The circuitry in this referenced article appears to permanently replace the bad word or bit line with one of the redundant lines.

The present approach provides for a replacement of a word or bit line with a redundant line by circuitry which is reversible. i.e., the "bad" line may be restored and the redundant line used to replace another "bad" line which is in a worse situation. For example, in a memory comprising a plurality of monolithic chips, we have a three-dimensional arrangement, the X and Y directions in the chip array and a third direction comprising common bit positions in a stack of chips which are in registration with each other. In reading out information stored on such common bit positions in the stack of chips, it is possible to use simple Hamming Code correction means to correct one error in the common bits being read. However, to correct more than one error by Hamming Code correction means becomes a highly complex and expensive proposition. Accordingly, it is possible to have a situation in a stack of chips wherein one line of common bits has one bit error, while another line has two or more bit errors. In such a situation, if two of the erroneous bits happen to turn up on the same chip, it is clear that in order to use error-correction potential most effectively, the erroneous bit which is in a line of common bits with only that error will be corrected by Hamming Code means, while the erroneous bit on a common bit line with more than one error will have to be corrected by the redundant l...