Browse Prior Art Database

Four Phase Per Eight Equal Clock Intervals Dynamic Logic Family and Layout Scheme

IP.com Disclosure Number: IPCOM000076515D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 4 page(s) / 57K

Publishing Venue

IBM

Related People

Thompson, GR: AUTHOR [+2]

Abstract

Fig. 1 shows a metal-oxide silicon (MOS) field-effect transistor (FET) three-stage inverter n channel system, which is operated by three out of a set of four clock-phase signals, including 01 applied to phase signal lines 10, 101, 02 applied to lines 19, 191 and 04 applied to lines 31, 311. The relative timing relationships between the clock-phase signals is shown in Fig. 2. The four clock-phase signals 01, 02, 03 and 04 are serially recurrent; they are spaced and do not overlap, so only one pulse is positive at a time; and they are consecutive always with intervening gaps. Alternate timing intervals from T0 to T10 include nothing or just one of the clock-phase signals. In practical applications, systems omit use of one or more clock-phase signals if they are unnecessary in a particular circuit.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 43% of the total text.

Page 1 of 4

Four Phase Per Eight Equal Clock Intervals Dynamic Logic Family and Layout Scheme

Fig. 1 shows a metal-oxide silicon (MOS) field-effect transistor (FET) three- stage inverter n channel system, which is operated by three out of a set of four clock-phase signals, including 01 applied to phase signal lines 10, 101, 02 applied to lines 19, 191 and 04 applied to lines 31, 311. The relative timing relationships between the clock-phase signals is shown in Fig. 2. The four clock- phase signals 01, 02, 03 and 04 are serially recurrent; they are spaced and do not overlap, so only one pulse is positive at a time; and they are consecutive always with intervening gaps. Alternate timing intervals from T0 to T10 include nothing or just one of the clock-phase signals. In practical applications, systems omit use of one or more clock-phase signals if they are unnecessary in a particular circuit. When the clock-phase signal Phi1 is positive at phase lines 10, 101 (which are connected together by means, not shown), from time T0 to T1 as indicated at 52 in Fig. 2, then stage 11 composed of FET's 12 and 13 is "precharged." The drain and gate of FET 12 are connected to terminal 10. The source of FET 12 and the drain of FET 13 are connected to output 14. The source of FET 13 is connected to line 101. The gate of FET 13 is connected to a terminal by input line 9. Stage 11 is precharged in the sense that output 14 connected to the source of FET 12 and drain of FET 13 is at a positive potential, and the stray capacitances on the output 14 are charged during that interval. After precharging has continued long enough to approach completion, the input potential at lines 10, 101 returns to a lower, quiescent potential value 53 at time T1. The subsequent potential at output 14 depends upon the potential at input line 9. If input line 9 is at a higher potential, the output line 14 will discharge rapidly, after precharge ends, through FET 13 which is gated on by the positive input. The output 14 is connected to the input 17 of stage 18, which includes FET's 20 and 21 connected (similarly to FET's 12 and 13) between lines 19, 191.

Precharging the input 17 of FET 21 grounds the output 22 of stage 18. This occurs when Phi1 is positive. The output 32 of a third FET stage 28, comprising FET's 29 and 30, will not be affected by precharging of input 17 by phi1 so the output 32 will remain valid, until second stage 18 is being precharged by clock- phase signal phi2.

There are three time intervals when the output of a circuit is not logically valid, in the sense that the data to be represented is obscured by dynamic circuit operations. The first such interval is during precharge. The second interval (conditional discharge) is immediately after precharge. It exists until the output of a stage can be discharged after the input of the stage has been charged. There is a third interval (unconditional discharge) from the time that the input to a stage is precharged, until its ou...