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Complementary Decoders

IP.com Disclosure Number: IPCOM000076521D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Spampinato, DP: AUTHOR

Abstract

Standard noncomplementary NOR block decoding requires the address and its complement, i.e., twice the number of address lines are required to select an address. Complementing the address can be avoided if complementary devices are used. The complementing function can be performed by a circuit arrangement formed from a plurality of N- and P-channel field-effect transistors, as shown in Fig. 1. The circuit shown is for the address location 10110. If this address is selected, the 2/4/, 2/2/, and 2/1/ lines are pulsed to the "1" level and the remaining lines are held at the "0" level. All devices are now OFF and the output rises to the supply voltage V(S). If another address had been selected, at least one of the FET devices of Fig. 1 would remain ON and the output would remain low.

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Complementary Decoders

Standard noncomplementary NOR block decoding requires the address and its complement, i.e., twice the number of address lines are required to select an address. Complementing the address can be avoided if complementary devices are used. The complementing function can be performed by a circuit arrangement formed from a plurality of N- and P-channel field-effect transistors, as shown in Fig. 1. The circuit shown is for the address location 10110. If this address is selected, the 2/4/, 2/2/, and 2/1/ lines are pulsed to the "1" level and the remaining lines are held at the "0" level. All devices are now OFF and the output rises to the supply voltage V(S). If another address had been selected, at least one of the FET devices of Fig. 1 would remain ON and the output would remain low.

The circuit in Fig. 2 is a dynamic version of that shown in Fig. 1. In this version, the address is selected, and the phase line phi is pulsed to a positive potential unconditionally charging all output lines through diode D1. Phase line phi is returned to ground and the selected address output remains high, since all devices are OFF; the remaining outputs all discharge through one or more ON devices of similar circuit arrangements. If, after each address selection, all address lines are returned to the 0 level, diode D1 (or an FET with gate connected to drain) is necessary at only one address location where all the devices in the NOR block are N-channel (00000 loca...