Browse Prior Art Database

FET Reliability Screening Test

IP.com Disclosure Number: IPCOM000076524D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Powlus, RA: AUTHOR

Abstract

A major consideration in field-effect transistor (FET) manufacture is the reliability of the gate oxide. Gate oxide reliability relates to electrical breakdown of the gate oxide insulator during accelerated temperature-electric field stress conditions. It is desirable to a) increase the length of time from the application of the stress conditions to the first gate oxide failure, and b) reduce the number of early gate oxide failures. The following technique provides improvements in both of these areas.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 71% of the total text.

Page 1 of 1

FET Reliability Screening Test

A major consideration in field-effect transistor (FET) manufacture is the reliability of the gate oxide. Gate oxide reliability relates to electrical breakdown of the gate oxide insulator during accelerated temperature-electric field stress conditions. It is desirable to a) increase the length of time from the application of the stress conditions to the first gate oxide failure, and b) reduce the number of early gate oxide failures. The following technique provides improvements in both of these areas.

The improvements are attained by prestressing the completed FET devices or circuits at an elevated temperature with no electric field in the gate oxide region; that is, With no voltages applied. The pre-stress temperature is in the order of 200-400 degrees C. The length of the pre-stress is in the order of 100 hours. Prestressing appears to convert the early gate oxide failures during accelerated temperature and electrical field stress (the reliability problem) to t(0) or initial failures (a yield problem). Since the early failures and time to first failure are prime reliability problems, prestressing reduces or eliminates the present early failure reliability exposure.

The above-described technique was experimentally verified by conducting an accelerated reliability test on linear FET's. Forty-eight devices were taken from the same wafer. Twenty-four of the devices were given a prestress at 300 degrees C (no voltages applied) for 100...