Browse Prior Art Database

Channel Attachment for a Small Processor

IP.com Disclosure Number: IPCOM000076542D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Berkebile, HE: AUTHOR [+3]

Abstract

Many of the smaller processors are designed to work with only a limited number of types of I/O devices and cannot be connected to the wide range of I/O equipment required to satisfy all customer requirements. The channel attachment diagrammed in the above feature will enable a small processor, such as IBM System 3 to communicate with and control the wide variety of I/O devices available for the large processing systems, such as IBM System/360 or System/370. The channel attachment design requires only two small processor instructions and does not need cycle-steal or interrupt capabilities.

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Channel Attachment for a Small Processor

Many of the smaller processors are designed to work with only a limited number of types of I/O devices and cannot be connected to the wide range of I/O equipment required to satisfy all customer requirements. The channel attachment diagrammed in the above feature will enable a small processor, such as IBM System 3 to communicate with and control the wide variety of I/O devices available for the large processing systems, such as IBM System/360 or System/370. The channel attachment design requires only two small processor instructions and does not need cycle-steal or interrupt capabilities.

In the drawing, the hardware of the channel adapter is indicated between the dotted lines and comprises a bus-out register 1 to supply an address to a channel interface indicated at 2. Bus-out register 1 is loaded by a load I/O instruction, channel bus 3 of the small processor through a gate 4 opened by a clock signal on line 5. After register 1 is loaded, a second clock signal on line 6 will gate a signal through gate 8 to signal line 9, to indicate data is on the signal- out bus. In response to the signals on the interface, the addressed I/O unit should transmit its address to the interface and raise an address-in line.

The next processor instruction is a sense I/O instruction. This instruction energizes a line 10 to gate ANDs 11 and 12 to set a flip-flop 13 to indicate the state of the signal line 14 which indicates if data (here devic...