Browse Prior Art Database

Transmission Speed Identification Scheme

IP.com Disclosure Number: IPCOM000076544D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Mitta, LA: AUTHOR

Abstract

The system set out in the drawing can determine the speed of transmission which will be used by a calling terminal. This will enable a processor to set itself to receive start-stop coded data at the indicated speed. The system requires that the first transmission from any terminal is an identification of the speed of transmission. The processor will count the number of transitions of the signal over a time period sufficient to enable the slowest terminal to send the speed identifying characters, and this number of transitions will be used to set the receiving speed.

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Transmission Speed Identification Scheme

The system set out in the drawing can determine the speed of transmission which will be used by a calling terminal. This will enable a processor to set itself to receive start-stop coded data at the indicated speed. The system requires that the first transmission from any terminal is an identification of the speed of transmission. The processor will count the number of transitions of the signal over a time period sufficient to enable the slowest terminal to send the speed identifying characters, and this number of transitions will be used to set the receiving speed.

In the drawing, an automatic answering modem 1 can be called over a common line 2 by any terminal of the system, so long as the processor, not shown, holds it available for data reception by maintaining a line 3 at a proper signal level. When the modem 1 is receiving a signal on line 2, it puts the decoded signal on line 4 to AND 5. During the waiting period, the processor will put a signal on a bus 6 to select the highest speed one of the decoding oscillators 7 for transmission to the sampling logic 8. Logic 8 will put a strobe pulse on input 9 to AND 5 for each sampling point.

The sampled data from AND 5 is supplied to a compare circuit 11 which compares the present sample with the last sample, to determine if there has been a transition in the signal level. This and the subsequent transitions of the sampled data are counted in a counter 12. A real-time count...