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OP Code and Status Handling for Emulation

IP.com Disclosure Number: IPCOM000076548D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Chang, FH: AUTHOR [+4]

Abstract

The drawing depicts logic for OP code and status handling when a system, such as the IBM System/370, is provided with a special feature for emulating another data-processing system. The IBM System/370 has an architecture which includes a number of addressable general purpose registers and floating-point registers, and includes a number of instruction formats including an SS format comprised of 48 binary bits, an RR format comprised of 16 binary bits, and an RS format comprised of 32 binary bits. When a base system is provided with an emulation feature, it has become common practice to specify a number of special instructions of the base system capable of performing the logic required by an instruction of the system being emulated.

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OP Code and Status Handling for Emulation

The drawing depicts logic for OP code and status handling when a system, such as the IBM System/370, is provided with a special feature for emulating another data-processing system. The IBM System/370 has an architecture which includes a number of addressable general purpose registers and floating- point registers, and includes a number of instruction formats including an SS format comprised of 48 binary bits, an RR format comprised of 16 binary bits, and an RS format comprised of 32 binary bits. When a base system is provided with an emulation feature, it has become common practice to specify a number of special instructions of the base system capable of performing the logic required by an instruction of the system being emulated. In the System/370, approximately 16 OP codes of the SS format instruction have been set aside for special emulation instructions.

When implementing emulation on a system, special hardware is usually provided for retaining status and control information peculiar to the system being emulated. When one of several jobs in a base data-processing system with multiprogramming capability is emulation, it is necessary that the special status and control information be saved and restored as the emulation job is interrupted and reinstated. For this purpose, a number of the base system registers, such as the addressable floating-point registers, can be utilized for the saving and restoring process. In this manner, the saving and restoring of the special emulator status can be accomplished using the standard interrupt handling capability of the base system control program.

In a system which includes a control store 1, base system microprograms will be contained in a portion 2 and microprograms for executing special emulator instructions will be contained in a portion 3. If it is desired to provide more special emulator instructions than provided by the OP codes set aside in the SS format instructions, the technique described in the drawing can be utilized.

In this regard, one of the allowed OP codes of the SS instructions is specified as the Emulator OP code (EMU OP code) contained in bits 0 - 7 of an instruction register 4. A number of flags are provided in bit positions 8 - 15 for the purpose of identifying the system being emulated, when the base system is capable of emulating more than one system. A check is made of the flags to insure that the instruction being decoded is for the system being emu...