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Associative Memory Cell

IP.com Disclosure Number: IPCOM000076558D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+3]

Abstract

The reversible character of search and read in an associative memory is used for the ready implementation of addressing by symmetrical PNP transistors.

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Associative Memory Cell

The reversible character of search and read in an associative memory is used for the ready implementation of addressing by symmetrical PNP transistors.

The associative-memory cell consists of the actual cell core for binary storage with cross-coupled storage transistors T1 and T2, load transistors T3 and T4, and two symmetrical PNP transistors T5 and T6 for addressing. The stand- by potentials of the array lines and of the bases of PNP transistors T5 and T6 at a particular switching state of the cell are shown in the figure.

During searching, a voltage pulse at about 0.8 V is applied to bit line B1 for interrogation of the binary 1. For interrogation of the binary 0 this pulse is applied to bit line B0. When the cell is in the 1 state, transistor T1 is conductive and the potential on the base of generator T6 vs 0.7 V, so that this transistor is inhibited. During interrogation of the binary 1 no current flows into word line WL1, i.e., no current on word line WL1 means "match". When the cell is in the 0 state transistor T6 is conductive, and during interrogation of the binary 1 current flows into word line WL1. Analogously, during interrogation of the binary 0, current passes through transistor T5 into word line WL1 when the cell is in the 1 state and no current when the cell is in the 0 state.

During reading, conditions are reversed. Current is impressed into word line WL1, a constant proportion of which for each cell, depending upon the sw...