Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Multichip Packaging

IP.com Disclosure Number: IPCOM000076559D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Ehret, P: AUTHOR [+3]

Abstract

Multichip packaging is used for high-packing densities of chips that are subject to relatively high-power dissipation. This type of packaging provides for a satisfactory thermal coupling of the chips to the cooling medium.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Multichip Packaging

Multichip packaging is used for high-packing densities of chips that are subject to relatively high-power dissipation. This type of packaging provides for a satisfactory thermal coupling of the chips to the cooling medium.

To ensure a good thermal conductivity, chips 1 are connected on their rear sides, via a eutectic gold silicon alloy 2, to substrate 3. Substrate 3 serves to discharge the heat produced as a result of the power dissipation and to make the package mechanically stable. Electrical connecting pins 4 pass through substrate 3 and are secured thereto.

The contact pads 5 on the top side of chips 1 are linked with multilayer substrate 6. Substrate 6 is designed to meet the requirements of low-capacity lines, since it is not used to cool the package nor to make it mechanically stable. Materials have approximately identical thermal expansion coefficients are employed for substrate 3 and multilayer substrate 6, to prevent the electrical connections to chips 1 from being unduly loaded.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]