Browse Prior Art Database

Interactive Instructional System

IP.com Disclosure Number: IPCOM000076579D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Featherston, JR: AUTHOR [+2]

Abstract

This instructional system is electrically compatible with conventional television systems and, therefore, can be used with present broadcast or closed-circuit television signals. Any video recording equipment capable of reproducing continuous standard television signals, either polychrome or monochrome, can also be used.

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Interactive Instructional System

This instructional system is electrically compatible with conventional television systems and, therefore, can be used with present broadcast or closed- circuit television signals. Any video recording equipment capable of reproducing continuous standard television signals, either polychrome or monochrome, can also be used.

The system affords student-to-tutor feedback in the present face-to-face learning situation; short-term means to assure the student mastery of an educational objective before proceeding to further dependent objectives; and ready response evaluation in sufficient detail to permit upgrading the materials of instruction.

A composite video signal applied at input terminals 10 is gated by a video- signal blanking circuit 14, for delivery to output terminals 20 to which a conventional television broadcast receiver is connected. Timing is recovered from the composite video signal in a conventional synchronizing pulse separating circuit 24. Horizontal and vertical synchronizing pulse trains are used to drive a stripe or sector generator 26 and associated stripe blanking format control circuitry 30. This control edits the composite video by enabling the gating circuit 14 so as to produce the desired display. Similar circuits, not shown, gate each of the audio-frequency signal channels.

The recovered TV synchronizing pulse trains drive a data clock circuit 32, which forms a 630 KHz data-bit clock burst at the proper time to shift each data block into a Data Block Shift Register 34. The data remains here until replaced 1/60 second later by the succeeding data block. Preferably, four parity positions 36 are provided for determining parity validity of each data block. This information is used to permit transfer out of Register 34 only if parity is satisfied. If parity is correct and the block address is that of a "control" word, the contents of the data block register 34 sets the state of the appropriate function co...