Browse Prior Art Database

Multiprocessing Storage Priority Network

IP.com Disclosure Number: IPCOM000076589D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Capowski, RS: AUTHOR [+3]

Abstract

When data is stored into or fetched from memory, in a uniprocessor environment (MP), the Storage Control Unit (SCU) has logic implemented in it such that a request will only be made to a nonbusy logical storage unit (assuming interleaving). Input/Output (I/O) devices and the Central Processing Unit (CPU) may simultaneously vie for storage priority. In a multiprocessor environment with two CPU's, it is required that each CPU be connected together such that each not only has the capability of accessing its own physically attached storage or storages and updating its own high-speed buffer, but also has the capability of accessing the other CPU's storages and invalidating the other CPU's high-speed buffer.

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Multiprocessing Storage Priority Network

When data is stored into or fetched from memory, in a uniprocessor environment (MP), the Storage Control Unit (SCU) has logic implemented in it such that a request will only be made to a nonbusy logical storage unit (assuming interleaving). Input/Output (I/O) devices and the Central Processing Unit (CPU) may simultaneously vie for storage priority. In a multiprocessor environment with two CPU's, it is required that each CPU be connected together such that each not only has the capability of accessing its own physically attached storage or storages and updating its own high-speed buffer, but also has the capability of accessing the other CPU's storages and invalidating the other CPU's high-speed buffer. If both CPU's work synchronously with a clock of period Xns but wire and circuit delays between CPU's are > Xns, a nonconventional priority network must be implemented to guarantee a unique CPU access to any storage on the system, and also guarantee accurate invalidation of the remote CPU's buffer, if installed.

This proposal makes it possible for storage to be accessed at a maximum rate of every machine cycle. 1) Both CPU's would operate using one clock for both machines. The period of this clock would be Xns. The priority networks in a unique machine would resolve priority every other Xns machine cycle. While both CPU's are running, one CPU will be resolving storage priority while the other machine's storage priority network is blocked. This implies that the two storage priority networks would alternate storage priority cycles and storage priority in a given CPU would be accomplished at a maximum rate of 2 Xns. 2) When a unique CPU determines through its priority mechanism which storage it wishes to access, it would send a signal (preselect) to the other (remote) CPU telling it which Logical Storage Unit (LSU) it wishes to communicate with. (Assume local CPU is CPU A and remote CPU is CPU B).

This LSU may be physically attached to any processor on the system. As CPU A sends its signal to CPU B, the following priority possibilities exist: Xns before CPU A resolved priority to select some LSU, CPU B selected a different or the same LSU that CPU A selected but, as of yet, CPU A has not received the preselects that CPU E sent to it. CPU B may not have selected any L/SU during its priority cycle.

The CPU Priority network, shown for CPU A in the selection of LSU 0, will basically work as that unit processor. While the CPU A Priority network is working in an MP environment during cycle A0, that is the storage cycle following selection by CPU B in cycle B0, you do not wish the store address register (STAR) or fetch address register (FAR) to access the storage bus. At T32B1, processor "A" will know which logical storage unit "B" had selected a...