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Division of Binary Oriented Numbers by Shifting and Comparing Technique

IP.com Disclosure Number: IPCOM000076590D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 4 page(s) / 65K

Publishing Venue

IBM

Related People

Chupay, JJ: AUTHOR

Abstract

The use of shifting and comparing for division of binary-oriented numbers to reduce computer operation time is discussed.

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Division of Binary Oriented Numbers by Shifting and Comparing Technique

The use of shifting and comparing for division of binary-oriented numbers to reduce computer operation time is discussed.

The most widely used computer method of dividing binary-oriented numbers has been and still is repetitive complementary addition. Disclosed is an implementation of a unique method of achieving division, by use of shifting and a comparing process. These two basic functions when used as described herein, will have an appreciable effect on the reduction of time. A gross description of the operation of such a method is as follows: The divisor is shifted and added to a register and that result is compared on a bit-by-bit basis, with the dividend. The quotient is generated from the shifts necessary to acquire the comparisons noted above.

The basic and principal hardware components of the shift and comparison method of dividing are shown, where blocks outside the dotted lines are duplicated for each binary-bit position.

The Divisor Register 10 A register that contains the divisor prior to the division procedure.

Shift Right (Trial Adder) 11 The shift component that will cause the divisor image in the shift register to be shifted one position to the right if the trial adder (m) result of the sum of the partial-dividend and divisor is greater than the dividend.

Shift Right (Carry) 12 The shift component that will cause the divisor image in the shift register to be shifted one position to the right, if a carry was generated during a trial-add and that carry could disturb the sequence of bits that are already in a compare status.

Shift Right (Compare) 13 The shift component that will cause the divisor image in the shift register to be shifted one position to the right, if a compare status is achieved between a bit in the partial-dividend register and a corresponding bit in the dividend register.

Shift Register 14 A register capable of shifting the divisor image either right or left. The shifting register should also be capable of outputting a copy of the divisor image at any position called for and leaving the original divisor image intact in the shift register for further shifting operations.

Trial-Adder 15 A conventional adder that test-adds the contents of the partial-dividend register and the contents of the shift register.

Shift Decoder 16 The capability of initially counting the total number of shifts necessary to align the divisor and the dividend at the high order and then decreasing the count as the division proceeds toward completion. As the count decreases and at specified times the decoder must insert bits into the quotient register as required.

Quotient Register 17 Quotient builds up toward final answer in register during division procedure.

The Partial-Dividend Accumulator 18 A register-adder combination

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that receives the divisor image and adds it to the contents of the register and retains the sum.

The TA Dividend 19 This...