Browse Prior Art Database

Control Cycle Technique

IP.com Disclosure Number: IPCOM000076600D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Bell, BC: AUTHOR [+2]

Abstract

This technique allows a central process unit (CPU) control cycle to be run with existing error-correction circuitry using uncorrected data with data definition.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 68% of the total text.

Page 1 of 2

Control Cycle Technique

This technique allows a central process unit (CPU) control cycle to be run with existing error-correction circuitry using uncorrected data with data definition.

Certain CPU memory types contain error-detection/correction circuitry to detect single and double-bit errors and correct single errors. This error detection/correction occurs some 100ns after memory access. This means that to maintain CPU performance the CPU control cycle must run with uncorrected memory data.

There are nonrecoverable operations which occur early in the CPU cycle and throughout the control cycle that must be blocked when the memory output (control decode) is invalid. To take an early error indication, sample it at a time in the CPU cycle that considers delay tolerances, (the memory being clocked separately in the particular CPU memory types) and try to block those nonrecoverable operations on the front end of the CPU cycle requires a major redesign of these early functions or lengthening of the CPU cycle to allow time to make the "go-no-go" decision.

To allow the CPU to run at its design speed and still perform the early nonrecoverable functions, the error indicator is defined and designed as a data indicator by resetting it to "Bad Data" at the beginning of every CPU cycle. This data indicator then transfers to the "Good Data" state at an internal memory design time, which allows the early CPU functions to occur on "Good Data" cycles and to be blocked on "Bad Data...