Browse Prior Art Database

SCR Transistor Memory Cell

IP.com Disclosure Number: IPCOM000076607D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Platt, S: AUTHOR

Abstract

This is a memory cell using Schottky diode decoding consisting of a silicon rectifier coupled to a transistor.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

SCR Transistor Memory Cell

This is a memory cell using Schottky diode decoding consisting of a silicon rectifier coupled to a transistor.

The memory cell of the figure basically is comprised of a silicon-controlled rectifier 10 cross-coupled to NPN transistor 11. The collector of the silicon- controlled rectifier is connected to a positive voltage source +V-1. Schottky sensing diodes 13 and 14 are connected between the silicon-controlled rectifier 10 and to a read/write bit line 15 and a write/bit line 16, respectively. An additional Schottky diode 17 is coupled across the silicon-controlled rectifier to keep it from saturating. Still another Schottky diode 18 is connected between the base and collector of transistor 11 to keep it out of saturation. A resistor 20 couples the emitter of the silicon-controlled rectifier 10 and the emitter of transistor 11 to a negative voltage -V-2.

In standby condition, the cell has two stable states. In the "1" storage state transistor 11 is conductive and in the "0" state it is nonconductive.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]