Browse Prior Art Database

Asynchronous Task Scheduler

IP.com Disclosure Number: IPCOM000076619D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Baudrion, C: AUTHOR [+3]

Abstract

A data-processing system refers to a bit sequence model to schedule a number of tasks of different priorities but at the same interruption level, usually base level. The tasks may be called for or cancelled by other tasks or by interruption level programs at any time by simple AND and OR operations. Tasks may run at more than one priority and may change their priority dynamically. The scheduler uses minimum storage and is rapid. It is particularly suited to machines with a left (right) justify and count instruction.

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Asynchronous Task Scheduler

A data-processing system refers to a bit sequence model to schedule a number of tasks of different priorities but at the same interruption level, usually base level. The tasks may be called for or cancelled by other tasks or by interruption level programs at any time by simple AND and OR operations. Tasks may run at more than one priority and may change their priority dynamically. The scheduler uses minimum storage and is rapid. It is particularly suited to machines with a left (right) justify and count instruction.

In a process-control system such as the IBM 2750 voice and data switching system, there are many short tasks with different priorities to be executed at the base level (i.e. no interruption level is assigned to these tasks). Each task is called for and cancelled independently, but at the end of each task the scheduler must always be ready to give control to the highest level called for.

The interruption level programs, as well as the base level tasks call for and cancel the tasks at any time. Core store and CPU time are severely limited. The CPU has AND, OR and LEFT-JUSTIFY-AND-COUNT operations.

The proposed task scheduler has been designed to operate in such an environment. Its principle consists in modeling the tasks on a sequence of bits whose order gives the priority. The value 1 means "called for", the value 0 means "cancelled". The bits are in 1-1 correspondence with a table of task entry addresses. Each time a task i...