Browse Prior Art Database

Shift Register Interconnection System

IP.com Disclosure Number: IPCOM000076621D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Ashany, R: AUTHOR [+3]

Abstract

Units of a data-processing system can communicate through a ring-structured network of shift register stages. Processors P, memories M, and other functional units F are interconnected by two shift register rings 1 and 2, each including several shift register stages 3 through 10. Stage 9 is shown in detail, the others are shown schematically with arrows indicating the flow of data through each stage. Any of the units P, M, F communicates with any other of these units by placing a message with appropriate control bits on ring 1 or 2, respectively. Each message includes a data section, an address section identifying the destination ring and unit, and a vacancy indicator.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Shift Register Interconnection System

Units of a data-processing system can communicate through a ring- structured network of shift register stages. Processors P, memories M, and other functional units F are interconnected by two shift register rings 1 and 2, each including several shift register stages 3 through 10. Stage 9 is shown in detail, the others are shown schematically with arrows indicating the flow of data through each stage. Any of the units P, M, F communicates with any other of these units by placing a message with appropriate control bits on ring 1 or 2, respectively. Each message includes a data section, an address section identifying the destination ring and unit, and a vacancy indicator.

Register stage 9 shown in detail, comprises a register 11 connected to the output of preceding stage 8 and a register 12 connected to the in: put of next stage 10. The ring advances in two steps in which all register stages operate at the same time. In the first step, data is transferred from preceding stage 8 to register 11 and from register 12 to next stage 10; registers 11 and 12 are isolated from each other and from their associated memory unit M. In the second step, data is transferred within the register stage from register 11 to register 12 or between registers 11 and 12 and associated unit M. Gate 13 couples the output of register 11 to the input of register 12 for transmitting messages through the stage. Gate 14 couples the output of register 11 to the input of buffer 16, which transmits messages to unit M. Gate 15 transfers messages that buffer 17 had accumulated from unit M to output register 12.

Gates 13, 14 and 15 are controlled by logic circuit 18 which receives control bits of the message from the output of register 11. Register 19 supplies the a...