Browse Prior Art Database

Fabrication of FET Structure

IP.com Disclosure Number: IPCOM000076629D
Original Publication Date: 1972-Mar-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Garnache, RR: AUTHOR [+3]

Abstract

This process provides extremely clean gate metal-oxide and semiconductor-oxide interfaces and improves thick-thin oxide threshold ratio.

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Fabrication of FET Structure

This process provides extremely clean gate metal-oxide and semiconductor- oxide interfaces and improves thick-thin oxide threshold ratio.

Referring to Fig. 1, semiconductor wafers 10 of the desired impurity type are placed in a reactor and successive layers of thin dielectric 12, polycrystalline semiconductor layer 14 and masking layer 16 are produced. These layers may be, for example, silicon dioxide, polysilicon and silicon nitride, respectively. The coated wafers are removed from the reactor and layer 16 is etched, utilizing a photoresist to define desired FET gate areas. Etched wafers are then placed in an oxidation furnace allowing exposed polysilicon layer 14 to be completely converted to silicon dioxide layer 14', as shown in Fig. 2, to provide thick dielectric protection in nondevice areas. After oxidation is complete, masking layer 16 is removed and a second polycrystalline layer is grown over the entire wafer. A masking step again defines the gate areas and all of layer 18 is removed except in the desired gate regions, as shown in Fig. 3. Source-drain areas are then etched down to the substrate surface. Thereafter, a doped oxide layer 20 is deposited and, in the same reactor, driven in to provide source-drain regions 22 and to dope the polycrystalline gate to increase its conductivity providing the structure shown in Fig. 4. Finally, the contact holes are etched and metallization applied in a normal manner.

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