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Memory Array Selection Technique

IP.com Disclosure Number: IPCOM000076632D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Pricer, WD: AUTHOR [+2]

Abstract

This memory cell selection technique minimizes interconnections and reduces cell area where integrated technology allows the fabrication of both bipolar and field-effect transistors (FETs). One such compatible process is called "Bifet". In most memory cell designs separate transistors or diodes, etc., are required to select each memory cell for reading or writing, as indicated by circuit diagram A. Where FET loads are used for bipolar drivers as in the arrangement shown at B, a novel selection technique is possible. This technique relies upon the high nonlinear impedances achievable with FETs.

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Memory Array Selection Technique

This memory cell selection technique minimizes interconnections and reduces cell area where integrated technology allows the fabrication of both bipolar and field-effect transistors (FETs). One such compatible process is called "Bifet". In most memory cell designs separate transistors or diodes, etc., are required to select each memory cell for reading or writing, as indicated by circuit diagram A. Where FET loads are used for bipolar drivers as in the arrangement shown at B, a novel selection technique is possible. This technique relies upon the high nonlinear impedances achievable with FETs.

All cells are quiescently biased at low-standby current where they dissipate little power and, because of the high-nonlinear source follower impedances of the FET loads, are very slow. When access to a cell is desired, the row containing the desired cell receives a much higher bias current. In the case of reading, the excess current allows the selected cell to be sensed in the presence of many smaller currents from nonselected cells. In the case of writing, the vastly increased bias makes the selected cell faster and, therefore, sensitive to the narrow bit writing pulse.

Operating margins may be improved by ceasing all bias on unselected cells while other cells are selected.

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