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Browse Prior Art Database

Class Metal Module to Chip Intersection

IP.com Disclosure Number: IPCOM000076641D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Balderes, D: AUTHOR [+2]

Abstract

A sputtered silicon dioxide or similar material layer 10 is used on the topside of a borosilicate glass-metal module 12, or similar device, prior to topside metallurgy deposition. The interconnecting vias 14 are built up by etching through the sputtered layer 10 to the module studs 13, which are for example plated copper, and depositing the desired terminal metallurgy in the vias. The solder 16 is evaporated onto this metallurgy and the semiconductor chip 18 is joined thereto by the solder reflow technique. Advantages include the microsocket location needed for accurate, yet simple chip joining and the use of the sputtered dielectric layer for metal-to-glass bonding improvement. Other metal patterns such as lands or fingers may be deposited on the layer 10 as well, after vias as opened and metallurgy formed thereon.

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Class Metal Module to Chip Intersection

A sputtered silicon dioxide or similar material layer 10 is used on the topside of a borosilicate glass-metal module 12, or similar device, prior to topside metallurgy deposition. The interconnecting vias 14 are built up by etching through the sputtered layer 10 to the module studs 13, which are for example plated copper, and depositing the desired terminal metallurgy in the vias. The solder 16 is evaporated onto this metallurgy and the semiconductor chip 18 is joined thereto by the solder reflow technique. Advantages include the microsocket location needed for accurate, yet simple chip joining and the use of the sputtered dielectric layer for metal-to-glass bonding improvement. Other metal patterns such as lands or fingers may be deposited on the layer 10 as well, after vias as opened and metallurgy formed thereon. The adhesion of metals, such as chromium or titanium, to the sputtered layer is well known and predictable.

The similarity of solder interfaces on both chip and module allows the size extendability and improves reliability. The quartz layer contains the borosilicate glass in proper stress during chip attachment at 340 degrees C to provide effective glass surface strengthening.

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