Browse Prior Art Database

Matrix Decoder with Read Only Memory

IP.com Disclosure Number: IPCOM000076645D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Henle, RA: AUTHOR [+4]

Abstract

With the described read-only memory (ROM) scheme, chip area occupied by the decoding circuits in a monolithic memory chip can be substantially reduced.

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Matrix Decoder with Read Only Memory

With the described read-only memory (ROM) scheme, chip area occupied by the decoding circuits in a monolithic memory chip can be substantially reduced.

In both the X and the Y decoders, a single transistor, e.g. T1, is utilized to represent a bit. A binary "1" is formed by a transistor with its base and emitter connected to a horizontal and a vertical line, respectively. A binary "0" is formed by a transistor with either its base or its emitter not connected. For simplicity, the "0" transistor are not shown. Each of the X and Y decoders also contain conventional true-complement (T/C) generators. Each of the Y lines include a load transistor T2, not required in the X.

Different ROM configurations are shown in the X and the Y decoders. All transistors in the X decoders share a common collector line (Vc) while in the Y decoders, collector sharing is limited to transistors located in the same column. Connected between the X and Y decoder matrices are conventional X and Y driver circuits shown schematically as 12 and 14, respectively.

In a ROM mode the cells comprise current switch emitter followers (CSEF), one of which is illustrated at 16. Of course, the memory cells can be readily altered so as to function in the random-access mode, and still be implemented by ROM type logic decoding matrices.

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