Browse Prior Art Database

Nondestructive Read and Regeneration Dynamic SCR Memory

IP.com Disclosure Number: IPCOM000076651D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Henle, RA: AUTHOR [+3]

Abstract

This monolithic memory cell operates in a random access dynamic mode with low power, high density, and fast access capabilities. The basic cell 10 comprises a monolithic silicon-controlled rectifier device (SCR) comprising a conventional NPN transistor 12 and a lateral PNP transistor 14 fabricated in the same monolithic bed. The biasing resistors R and the diode D are formed as discrete devices. In order to compensate for probe loading, a discrete capacitor 16 of between 7 and 10 picofarads, is connected between the collectors of the transistors 12 and 14.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Nondestructive Read and Regeneration Dynamic SCR Memory

This monolithic memory cell operates in a random access dynamic mode with low power, high density, and fast access capabilities. The basic cell 10 comprises a monolithic silicon-controlled rectifier device (SCR) comprising a conventional NPN transistor 12 and a lateral PNP transistor 14 fabricated in the same monolithic bed. The biasing resistors R and the diode D are formed as discrete devices. In order to compensate for probe loading, a discrete capacitor 16 of between 7 and 10 picofarads, is connected between the collectors of the transistors 12 and 14.

Accessing or reading and writing of the cell is accomplished by providing suitable control pulses to the terminals EX1, EX2 and EY. The state of the output cell is sensed at output terminal VO.

Operatively, the cell consumes an extremely negligible amount of power because it does not draw power during the quiescent state. The voltage level diagram illustrates the manner in which the signals are applied to a cell for the following accessing operations: a write 1 (W-1); a read 1 (R-1); erase; write 0 (W- 0); and read 0 (R-0). The signal applied to the EX2 terminal is also used to regenerate the information in the cell. The state of the output cell during the different accessing operations is depicted by the voltage diagram VO.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]