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Browse Prior Art Database

Memory Cell with Write Switch Transistors

IP.com Disclosure Number: IPCOM000076657D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Bleher, JH: AUTHOR [+2]

Abstract

Prior "nanoamp" monolithic memory cells which comprise transistors PNP1 and PNP2, EF1 and EF2 as well as cross-coupled transistors NPN1 and NPN2, tends to develop high bit line current during the write operation.

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Memory Cell with Write Switch Transistors

Prior "nanoamp" monolithic memory cells which comprise transistors PNP1 and PNP2, EF1 and EF2 as well as cross-coupled transistors NPN1 and NPN2, tends to develop high bit line current during the write operation.

The present modification avoids this problem. The drawing shows the modified memory cell configuration which consists of the nanoamp cell supplemented by two write switch transistors NPN3, NPN4 and by two Schottky barrier diodes SBD1, SBD2. The purpose of the SBD's is to prevent the cross- coupled transistors from deep saturation, in order to increase the switching speed.

The read operation is the same as with the nanoamp cell; the excellent read performance of this cell is therefore also the same. However, the disadvantage of the high bit line current during write operation of the nanoamp cell has been eliminated by introducing the two write switch transistors. The additional area required in a monolithic memory cell is very small, since the two transistors can be integrated into the isolation pockets of the cross-coupled transistors NPN1, NPN2; there is also no additional metallization required.

The write operation is performed by applying a negative pulse at the word select line and a positive pulse at the corresponding read/write line B0 or B1; e.g. transistor NPN1 is turned off by a positive pulse at the read/write 1 line, turning on transistor NPN4 to take over the base current of transistor NPN1. The minim...