Browse Prior Art Database

Alterable Read Only Memory

IP.com Disclosure Number: IPCOM000076682D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Zechman, JH: AUTHOR

Abstract

Read-Only Memory (ROM) 1 has an array, partially shown, of storage cells 00, 10, etc. Each cell has an electroplatable transparent conductive film region 2 superimposed over a pair of photodiode sensors 3. Depending on the convention selected, when plated the particular film region 2 represents one binary state, e.g., "1" and when not plated represents the other binary state, e.g., "0". In operation, the ROM is read out by an appropriate light source, which may be of the flood or scanning type.

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Alterable Read Only Memory

Read-Only Memory (ROM) 1 has an array, partially shown, of storage cells 00, 10, etc. Each cell has an electroplatable transparent conductive film region 2 superimposed over a pair of photodiode sensors 3. Depending on the convention selected, when plated the particular film region 2 represents one binary state, e.g., "1" and when not plated represents the other binary state, e.g., "0". In operation, the ROM is read out by an appropriate light source, which may be of the flood or scanning type.

The photodiode sensor pairs of each cell are diffused in a substrate 4, e.g., P-type substrate of Si. For each cell there is also a pair of control diodes 5 diffused in the isolation N-type region 6. Also diffused in substrate 4 are the transistor 7 and diode 8 used in the plating and deplating of the film 2. An insulation layer 9, e.g., layer of SiO(2), insulates the metal, e.g., Aa, conductive pattern 10 which includes the readout conductors, e.g., R1X-R1Y, and the control conductors, e.g., W1X and W1Y, that are connected to the photosensor diodes 3 and control diodes 5, respectively. Metal conductive pattern 10 also includes the +V and ground bias conductors. To minimize crossovers, diffused undercrossings, e.g., undercrossing 11, are provided at various places in substrate 4. Insulation layer 9 also insulates the conductive pattern 10 from the control circuitry 7, 8, and 12 used in the plating and deplating operation. Resistor 12, shown schem...