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Circuit Response Time Tester

IP.com Disclosure Number: IPCOM000076702D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Deckert, ME: AUTHOR

Abstract

A "go-no-go" tester for determining the response time of circuits following the occurrence of an excitation pulse (for example, the response time of a read-only memory to an interrogation pulse) is shown. Provision is included for rejecting tested circuits falling within a determinable portion of the known statistical curve representing the response time of a large number of tested circuits of the same kind.

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Circuit Response Time Tester

A "go-no-go" tester for determining the response time of circuits following the occurrence of an excitation pulse (for example, the response time of a read-only memory to an interrogation pulse) is shown. Provision is included for rejecting tested circuits falling within a determinable portion of the known statistical curve representing the response time of a large number of tested circuits of the same kind.

A pulse which is simultaneous with the circuit excitation pulse is applied to line 1 and through variable delay circuit 2 to AND circuit 3. The output pulse from the circuit under test in response to the excitation pulse is applied to line 4. The pulse on line 4 is routed directly to a first input of exclusive OR circuit 5 and, via fixed-delay circuit 6 and invertor 7, to a second input of circuit 5.

Exclusive OR circuit 5 produces an output pulse having a leading edge simultaneous with the occurrence of a pulse on line 4 and a trailing edge occurring thereafter, following an interval equal to the delay of fixed-delay circuit 6. AND circuit 3 produces a "no-go" output on line 8 whenever the pulse from exclusive OR circuit 5 coincides with the delayed excitation pulse at the output of circuit
2.

Variable delay 2 is set to a time, based upon the known statistical distribution of response times of the circuits to be tested, when substantially all the tested circuits can be expected to have produced an output following the occurrence...