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Browse Prior Art Database

Multipulse Logic Simulation for Use in AC Testing

IP.com Disclosure Number: IPCOM000076707D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Chao, CC: AUTHOR

Abstract

The present system provides for simulated testing of integrated circuits for AC parameters such as rise time, fall time and circuit delay. In testing for such AC parameters, an essentially DC type of signal pattern is applied in parallel to inputs 1-4 of the three-level logic integrated circuit simulation shown in Fig. 1. By appropriately changing the DC value in each pattern increment, the overall pattern is, in effect, an AC pattern. The three-level logic simulation may be that described in Patent No. 3,633,100, which simulation is implemented in double-rail logic.

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Multipulse Logic Simulation for Use in AC Testing

The present system provides for simulated testing of integrated circuits for AC parameters such as rise time, fall time and circuit delay. In testing for such AC parameters, an essentially DC type of signal pattern is applied in parallel to inputs 1-4 of the three-level logic integrated circuit simulation shown in Fig. 1. By appropriately changing the DC value in each pattern increment, the overall pattern is, in effect, an AC pattern. The three-level logic simulation may be that described in Patent No. 3,633,100, which simulation is implemented in double- rail logic. However, if such a double rail logic scheme is used, it should be understood that the simulation should also include means for converting single- rail inputs 1-4 to double-rail logic, and for converting the double-rail logic outputs into the single-rail outputs shown, W-Z.

A simple illustration of an AC input test pattern and the resulting output pattern is shown in Fig. 2. The principle by which this system operates is the superposition of DC simulation per unit time to achieve AC simulation. All inputs in terms of pulses and DC biases are sectionalized into time units. Each time unit may be assumed to be the propagation delay involved in a single-logic block within the integrated circuit chip being simulated. Since an integrated logic circuit chip normally consists of the same type of logic circuit blocks, this propagation delay should be relativel...