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Browse Prior Art Database

Electroless Plating for Interconnections

IP.com Disclosure Number: IPCOM000076711D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Cowell, DR: AUTHOR [+3]

Abstract

This technique eliminates high-temperature thermal cycling for integrated circuit pin attachment. An electroless copper bath 10 is introduced into vessel 12 via an input valve 14. A semiconductor substrate 16 contains a plurality of copper land patterns 18. A plurality of copper pins 20 are aligned and positioned by a rigid jig assembly comprising an apertured TEFLON* plate 22 and a soft spongy liner 24. The jig assembly positions and supports the plurality of pins 20 and also contains the plating solution in the lower chamber. The pin heads are of a pointed design to insure that the plating buildup moves up from the geometric center to a complete 360 degrees, so as to eliminate any voids in the structural integrity of the plating operation. * Trademark of E. I. de Pont de Nemours & Co.

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Electroless Plating for Interconnections

This technique eliminates high-temperature thermal cycling for integrated circuit pin attachment. An electroless copper bath 10 is introduced into vessel 12 via an input valve 14. A semiconductor substrate 16 contains a plurality of copper land patterns 18. A plurality of copper pins 20 are aligned and positioned by a rigid jig assembly comprising an apertured TEFLON* plate 22 and a soft spongy liner 24. The jig assembly positions and supports the plurality of pins 20 and also contains the plating solution in the lower chamber. The pin heads are of a pointed design to insure that the plating buildup moves up from the geometric center to a complete 360 degrees, so as to eliminate any voids in the structural integrity of the plating operation. * Trademark of E. I. de Pont de Nemours & Co.

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