Browse Prior Art Database

Predicting SiO(2) Failure Rates from Oxide Defect Densities

IP.com Disclosure Number: IPCOM000076715D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 4 page(s) / 21K

Publishing Venue

IBM

Related People

Amendola, A: AUTHOR [+3]

Abstract

The dominant failure mode of the passivation layers on integrated circuit chips has been seen to be cation migration through oxide defects. Traditionally, the methods for testing and evaluating the reliability of the passivation consisted of temperature and humidity stress testing, extrapolating to use conditions via acceleration factors, and using lognormal failure rate equations. The model presented here is a result of a correlation of this kind of data with defect data, which enables projections without stress testing.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 4

Predicting SiO(2) Failure Rates from Oxide Defect Densities

The dominant failure mode of the passivation layers on integrated circuit chips has been seen to be cation migration through oxide defects. Traditionally, the methods for testing and evaluating the reliability of the passivation consisted of temperature and humidity stress testing, extrapolating to use conditions via acceleration factors, and using lognormal failure rate equations. The model presented here is a result of a correlation of this kind of data with defect data, which enables projections without stress testing.

The standard method for evaluating the reliability of sputtered SiO(2) passivation has many disadvantages which make it impractical to use as an effective tool: it takes too long, exact median time to failure can not be obtained, failure analysis is slow and costly and too few fails are seen during tests of several thousand hours.

Detecting defects with the present method is accomplished by means of decoration of metal by a chemical etch. In order to relate defect data to life-test data, a large life-test data base is needed.

Results were gathered from a large scale evaluation test that was run concurrently with the defect work. The test consisted of test chips flip-chip mounted by standard solder process to a 16-pin substrate. The chips came from 4 different sputtering runs. The sputtered SiO(2) thickness was 3 microns and the aluminum thickness was 20KA. The test conditions were environmental stress of 85 degrees C and 80% relative humidity with a 15 volt bias between three solder terminals and 3 adjacent strips on each chip. The test was run for a total of 3000 hours with readouts at 500 hour intervals.

Briefly, the results of this test showed that failures induced followed a lognormal distribution in time with sigma = 1.83.

Unstressed chips from the same four sputtering runs were obtained for defect analysis and correlation with life test results. The chips obtained were subjected to the standard 2, 5, 15 minutes HCl immersion and observation. Each defect was charted on a drawing of the test vehicle for later analysis.

Since a defect had to be near a Pb/Sn pad to cause a failure by the proposed mechanism, "critical edge length" was defined as that edge of metal stripe that was within one mil of a Pb/Sn pad. The SiO(2) defects that were within the critical edge were called "critical defects". By comparing critical defects detected by HCl immersion with environmental test fails from the same population, it was observed that 2% of the chips had critical defects after two minutes in HCl and about 2% of the chips failed on test after 1000 hours. From this observation, it appeared that virtually every critical defect that is detectable by a two-minute immersion in 18% HCl lead to a device failure in 1000 hours of stress.

The analogy between time to device failure on test and time to defect detection in HCl etch was carried a step further. Life test is usua...