Browse Prior Art Database

Programmable Read Only Memory Stack Gate FET

IP.com Disclosure Number: IPCOM000076720D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Chiu, TL: AUTHOR

Abstract

In this memory device a second gate over a high resistivity Polysilicon floating gate is provided. Electrons can be stored in the floating gate and their absence or presence can be used to indicate binary information.

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Programmable Read Only Memory Stack Gate FET

In this memory device a second gate over a high resistivity Polysilicon floating gate is provided. Electrons can be stored in the floating gate and their absence or presence can be used to indicate binary information.

The single cell field-effect transistor (FET) has two spaced P+ diffused regions 10 and 12 in an N- substrate 14. A thick layer 16 of oxide overlies substrate 14 except in the gate region where a thinner oxide layer 18 is provided. Overlying SiO(2) layer 18 is a N- polysilicon layer 20 which constitutes a floating gate. Layer 22 of Si(3)N(4) is deposited over layer 16 and gate 20. Electrodes 24 and 26 are provided having ohmic contact with reasons 10 and 12, and a second gate electrode 28 is provided over floating gate 20. An electrode 30 is provided on the backside of substrate 14. In use the aforedescribed structure will be embodied in a suitable matrix.

To write information, a large negative voltage pulse is applied across electrodes 26 and 30. When the voltage is close to the avalanche voltage of the P+, N- junction, electrons are injected into the N- polysilicon gate 20. To read information, that is the absence or presence of electrons in gate 20 a negative pulse is applied across electrodes 24 and 26. When electrons are stored in gate 20 an inversion channel is formed between regions 10 and 12 and current will flow. If no electrons have been stored no inversion channel is created and no current will...