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One Device Memory Cell with Step Oxide Structure

IP.com Disclosure Number: IPCOM000076723D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Chiu, TL: AUTHOR

Abstract

With this one-device memory cell high-package density can be achieved, also, it cam be used in either binary or ternary systems.

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One Device Memory Cell with Step Oxide Structure

With this one-device memory cell high-package density can be achieved, also, it cam be used in either binary or ternary systems.

The cell 10, having the structure shown, is arranged in a memory matrix with bit lines 12 and word lines 14 connected in the conventional manner. The cell structure per se consists of a substrate 16 having a diffusion 18 beneath an ohmic contact with a charge injection electrode 20 connected to bit line 12, and a second diffused region 22 located beneath charge storage electrode 24 connected to word line 14. Electrode 24 is separated from the substrate 16 by a layer of oxide 26, which is relatively thin over the region 22 and has a thicker portion 27 between regions 18 and 22.

In the binary mode of operation, the absence or presence of a charge located under electrode 24 is used to indicate a "1" or a "0".

When a charge is transferred during either read or write operation a voltage is applied to word line 14, which exceeds the threshold voltage of the portion of the electrode over oxide layer 27 forming a channel between regions 18 and 22. In holding state, the voltage is lowered to a value slightly beneath the threshold voltage which is sufficient to hold charges within region 22. Suitable voltages, which are synchronized with the aforementioned voltages, are applied to the bit line 12 and word line 14 during the write operation. A suitable sensing means senses whether or not charges are...