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Semiconductor Mask and Wafer Alignment

IP.com Disclosure Number: IPCOM000076756D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Chu, J: AUTHOR [+2]

Abstract

Shown is a method utilizing a square bull's-eye alignment pattern in the kerf area of a wafer for mask and wafer alignment prior to exposure.

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Semiconductor Mask and Wafer Alignment

Shown is a method utilizing a square bull's-eye alignment pattern in the kerf area of a wafer for mask and wafer alignment prior to exposure.

For the first masking level of any device, there is one bull's-eye pattern (small square within a large square) on the mask and none on the wafer. This pattern is transferred to the wafer by etching in accordance with conventional photolithographic techniques.

For the second masking level of any device, there is one square pattern on the mask and the bull's-eye pattern on the wafer. Alignment is achieved by placing the pattern on the mask between the two squares of the bull's-eye pattern formed on the wafer.

In the third masking level of any device, the mask is provided with two square bull's-eye patterns of which only one is used for alignment of the mask to the wafer, with the other bull's-eye used for alignment in the fourth masking level, after a freshly etched pattern is available. During the fourth masking level of any device, the mask contains one square and the alignment is carried out on the freshly etched bull's-eye similar to the alignment in the second masking level.

The above may be repeated for any number of masking levels, with freshly etched wafer alignment patterns for each level.

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