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Overlapped Dual Access Instruction Store

IP.com Disclosure Number: IPCOM000076765D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Leppala, RA: AUTHOR

Abstract

The overlapped dual-access instruction store includes even and odd memories which are accessed alternately in an overlapped manner, whereby data from one of the memories is being processed while data from the other memory is being accessed. This arrangement permits the memories to be relatively slow and still provide an average access time, whereby the data byte from memory is ready for use at approximately the access speed of the memory. The access time is reduced only when branching conditions occur. This is because the data fetched ahead of time cannot be used for a branch operation.

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Overlapped Dual Access Instruction Store

The overlapped dual-access instruction store includes even and odd memories which are accessed alternately in an overlapped manner, whereby data from one of the memories is being processed while data from the other memory is being accessed. This arrangement permits the memories to be relatively slow and still provide an average access time, whereby the data byte from memory is ready for use at approximately the access speed of the memory. The access time is reduced only when branching conditions occur. This is because the data fetched ahead of time cannot be used for a branch operation.

The addresses for addressing the memories 10 and 15 originate in Program Address Register 20, which is a binary counter advanced by pulses from clock
25. The starting address is normally set by resetting register 20 or it can come from manually settable data switches 26. The address from data switches 26 are set into 20 via AND circuit 28 and when a branch condition occurs, addresses from 27 are sent to 20 via AND circuit 29. With the initial starting address in 20, the address is then transferred to even address register 30 and appropriate clock time, even control logic 35 takes the address from 30 into even address register 36 and also conditions controls 37 for accessing even memory 10. The data fetched from 10 is stored in buffer 38.

While memory 10 is being accessed, the address in 30 is transferred to register 40. The address in 40 will be transferred to address register 46 when odd control logic 45 is conditioned by trigger 21. Control 47 is also rendered active by control 45. The data fetched from memory 15 is entered into buffer 48. The data in buffers 38 and 48 are passed to the output via assembler logic 50 at the appropriate clock times. It should be n...