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Logical Assembly Testing System

IP.com Disclosure Number: IPCOM000076778D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 4 page(s) / 66K

Publishing Venue

IBM

Related People

Millham, EH: AUTHOR [+2]

Abstract

This system automatically tests logical assemblies. It employs computer generated testing instructions, automatic fault location and rework information. Testing instructions are generated by a series of computer algorithms from a digital logic and physical description of each assembly and subassembly (or components). Test sequences contained within the testing instructions are applied to the assembly by a logic and delay testing machine which in addition controls an automatic probing mechanism that collects error data, calculates and defines fault locations and provides rework information.

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Logical Assembly Testing System

This system automatically tests logical assemblies. It employs computer generated testing instructions, automatic fault location and rework information. Testing instructions are generated by a series of computer algorithms from a digital logic and physical description of each assembly and subassembly (or components). Test sequences contained within the testing instructions are applied to the assembly by a logic and delay testing machine which in addition controls an automatic probing mechanism that collects error data, calculates and defines fault locations and provides rework information.

Referring to Fig. 1, a general purpose computer is used as the test data computer 1. Primary data input is by tape 5 although additional entry, primarily for manual intervention, may be by punched card 6. Information and testing instructions are placed on tape 9, punched card 10, or directly to the tester control 2 as well as on printer 7. The tester control 2, which is also a general purpose computer, communicates back to the test data computer 1 directly or through tape 9 or punched card 10 for testing improvements, status, and product failures. Test data from the test data computer 1 is stored on disk 11 for application through the testers 1 to N to the product. Results of testing are indicated on tape 9, printer 12, and punched card 10. Operator instructions are output on console typewriter 8 which also allows full control and monitoring of all tester functions.

Each tester 1 to N contains decode logic, delay measuring circuits, probe controls, cooling and all other environmental type requirements necessary to interface the product with the test system.

The test data generation computer, Fig. 2, receives all necessary information about the logical and physical product and records it on tape 1. This information is compiled by the setup algorithm 5 into tables for use by other algorithms. These tables are modified and extended by the macro algorithm 6 which, from information contained on the macro-disk file 3, further describes certain more complicated circuits into manageable entities. The logic build algorithm 7 uses the setup tables to produce logic tables, which describe the logical product and stores these tables on the in-process file 11. Similarly, the physical build algorithm 8 describes and tabulates the physical properties of the product. The in-process file 11 provides the data base for various algorithms, as well as interfacing manual input 10 and tester feedback information 9. Delay build 12 constructs a delay model of the product using the previously constructed logic and physical models, and certain component information contained on the component file 4 and input on the component information tape 2. The delay build algorithm 12 uses as a basis of construction the delay calculation algorithm 13, which is a product oriented set of delay rules and equations.

The stimulus response main algorithm 14 c...