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Fixed Increment Pauses for Variable Cycle Clock

IP.com Disclosure Number: IPCOM000076779D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Bloom, EM: AUTHOR [+2]

Abstract

This system provides selective fixed increment pauses for each of the selectable basic machine cycles provided by a variable-cycle clock, without changing intermediate clock timings within the CPU cycle. One such clock is described in "CLOCK," R. J. Carnevale and L. D. Howe, IBM Technical Disclosure Bulletin, Vol. 12, No. 1, June 1969, pages 71-73.

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Fixed Increment Pauses for Variable Cycle Clock

This system provides selective fixed increment pauses for each of the selectable basic machine cycles provided by a variable-cycle clock, without changing intermediate clock timings within the CPU cycle. One such clock is described in "CLOCK," R. J. Carnevale and L. D. Howe, IBM Technical Disclosure Bulletin, Vol. 12, No. 1, June 1969, pages 71-73.

The present system replaces the oscillator of the last-mentioned clock. It provides four selectable pause increments of 0, 22.5 nanoseconds (ns), 45.0 ns and 67.5 ns time periods. Thus, when combined with each of the three cycle lengths of 180, 225 and 270 ns provided by the original clock, the clock has an extended capability of providing a total of twelve different machine cycles. The system is hereinafter sometimes referred to as oscillator. The selected pause is injected at the trailing end of each cycle, i.e. before the beginning of the next cycle.

A pause is defined as the length of time equal to one-half the period of twice the oscillator frequency, or one-quarter the period of the output oscillator frequency when it is free running.

In operation, a signal is applied to input A with twice the frequency desired for the basic oscillator frequency. Input B is activated by a signal ODD PAUSE when the desired number of pauses is odd for any given cycle, e.g. 22.5 or 67.5 ns. A GO signal is applied to input C from the central processing unit (CPU) system, being clocked to run the oscillator control circuit portion of oscillator 10. When the CPU system is stopped, the oscillator output is free running but the GO signal is inactive.

A signal PAUSE CYCLE activates input D whenever any pause is desired. When inactive, the oscillator output signal is an uninterrupted symmetric signal.

Input E is activated by a signal TWO PAUSES, when the length of pause desired is two times the length of one pause.

Input F is activated by signal ONE PAUSE when one pause is desired.

Phase inverter 1 provides 2 times oscillator input. Phase inverter 2 provides a drive signal for frequency divider 7. Phase inverter 3 provides system oscillator output. Logic 4 inverts phase of 2 times oscillator used to drive frequency divider
7. Flip-flop 5 is triggered when logic 4 is active at end of cycle.

AND/OR logic 6 decides which phase of 2 times oscillator will drive frequency divider 7 and turn off system oscillator when pause 16 is active. Start-up flip latch 8 synchronizes the setting of oscillator-run latch 9. Oscillator-run latch 9 is on when oscillator is clocking the system, and is off when oscillator is not clocking the system and the oscilla...