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Browse Prior Art Database

Video Character Handling Display Attachment

IP.com Disclosure Number: IPCOM000076797D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Boyd, WW: AUTHOR [+2]

Abstract

In a display system in which five lines are to be displayed, normally a one-character buffer is required between the refresh buffer and the dot generator for each line.

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Video Character Handling Display Attachment

In a display system in which five lines are to be displayed, normally a one- character buffer is required between the refresh buffer and the dot generator for each line.

The number of buffers can be reduced to two, as illustrated, if the timing sequence shown is followed. Five waveforms are shown. When vertical retrace (VRTR) is up, no input to the display occurs. When VRTR is down, input to the display as illustrated by trace line one TL1; TL2, etc. occurs. The clock phi gates data to and from the single-character buffers. For purposes of operational description, assume character L1 is in the one-character buffer adjacent the read-only store (ROS) and character L2 is in the one-character buffer adjacent the refresh buffer (RB). At the first clock, L1 is shifted to the ROS and L2 into the other single-character buffer. On the first SETDOT pulse the L1 character dots for that particular sweep are latched up in a dot buffer. No display has however taken place since VRTR is high. When VRTR falls display is allowed, and the L1 character dots are clocked out between the first and second SETDOT pulses. At the second SETDOT pulse the L2 character dots are latched up in the dot buffer, and are subsequently clocked out between the second and third SETDOT pulses. This sequence continues with the memory being read once for each line, until line five has been displayed. Vertical retrace then occurs and the sequence is repeated unti...