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Bit Line Powered Storage Cell

IP.com Disclosure Number: IPCOM000076830D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+2]

Abstract

The storage cell has associative characteristics and a high-operating speed, in spite of the low-surface requirements of the monolithic integrated layout and its low standby power.

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Bit Line Powered Storage Cell

The storage cell has associative characteristics and a high-operating speed, in spite of the low-surface requirements of the monolithic integrated layout and its low standby power.

The actual storage cell consists of a cross coupled transistor flip-flop T1 and T2. Transistors T3 and T4 with commoned bases, which are complementary to cell transistors T1 and T2, serve as load elements. To each cell coupling point a and b the emitter of a transistor T5 or T6 is connected. The emitters of T5, T6, T1, and T2 are of the same conductivity type. Collects of T5 and T6 are linked with a word search line WS via resistor R. The bases of T5 and T6 are connected to associated bit lines B1 and B0, respectively.

For reading, the two word line potentials WU and WL are lowered. Simultaneously, the two bit line potentials are raised by currents being fed into the bit lines, so that the potentials of the bit lines become a function of the potentials of the cell coupling points a and b. The current fed into the cell is limited by resistor R and the bit line currents.

For writing, the two word line potentials WU and WL are lowered. However, in this case, the voltage of only one big line B0 or B1 is made positive, so that current flows into only one cell coupling a or b, which leads to the cell adopting a defined state.

During searching, the bit line voltage is raised to a lower value than that used for writing, so that the corresponding cell coupling poin...