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Modeling Memory Modules

IP.com Disclosure Number: IPCOM000076849D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 6 page(s) / 150K

Publishing Venue

IBM

Related People

Dubler, JF: AUTHOR [+2]

Abstract

The flow charts specify the operation of a memory model. The following description of the memory operation illustrates the process. During simulation logic block calculations are scheduled and executed in normal simulator mode (which may be zero-delay, unit-delay, nominal delay, etc.). At the beginning of each simulation time, the memory queue is checked to see if it contains any actions for the present time (i.e. if the next queue entry is for the present time). If any memory actions are found they are executed and logic simulation proceeds.

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Modeling Memory Modules

The flow charts specify the operation of a memory model. The following description of the memory operation illustrates the process. During simulation logic block calculations are scheduled and executed in normal simulator mode (which may be zero-delay, unit-delay, nominal delay, etc.). At the beginning of each simulation time, the memory queue is checked to see if it contains any actions for the present time (i.e. if the next queue entry is for the present time). If any memory actions are found they are executed and logic simulation proceeds.

When a changing logic value is propagated to a memory input a number of events occur. If the change is on a data-in or address line the operations detailed in A and B result. The changing environments are determined, the block values are updated, bits are set off in T1 and T3 tables to indicate the changing environments, and T1 or T2 and T3 or T4 actions are scheduled in the queue at the present time plus t1 or t2 and t3 or t4, respectively. When the actions scheduled are subsequently executed, the environments that have not changed since the sections were scheduled will have bits set on in the T1 or T3 tables to indicate they have not changed. The details of the process involve placing the input block identification, a mask of the changing environments, and the present block value in the queue entry (this is a typical T1-type queue entry). When the entry is executed the block value in the queue is compared with the present block value to determine if they are the same. If the values are the same, it indicates that the input has not changed since the queue entry was created. An exception to this occurs only when the input line has changed several times. In this case it is assumed that the average value has been equal to the final value. The mask of changing environments is used to reset the T1 or T3 tables for the input blocks, whose values are equal to the values in the queue. The overall result of this process is that the T1 and T3 tables always indicate which environments of the input blocks have changed in t1, t2, and t3, or t4 time units prior to the present time. A similar process occurs when an input change is propagated to a read or write control line (C and F). Here the RCTL or WCTL locations in the T3 table are set for changes that start memory operations and T6'R or T6'W actions are scheduled at the present time plus t6' (t5 + t6) to reset the table. Thus the T3 table RCTL and WCTL locations always indicate which environments of the read and write control lines have changed in t5 + t6 time units prior to the present time.

In addition to scheduling events to maintain data in the T3 table, changes to the read or write control lines initiate all subsequent memory operations (as shown in C through I). When an input change is propagated to a read or write control line the resulting operation may schedule T3R/W, T4R/W, T5R/W, T6' R/W, T6''R/W and T9R/W actions (C)...