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Browse Prior Art Database

Central Processing Unit Only Backing Store

IP.com Disclosure Number: IPCOM000076855D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Beausoleil, WF: AUTHOR [+3]

Abstract

The speed of a memory cam be improved by having a central processing unit (CPU) 10 be able to interrogate both a buffer 12 and a main store 14, while having the I/O 16 be capable of only interrogating the buffer 12.

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Central Processing Unit Only Backing Store

The speed of a memory cam be improved by having a central processing unit (CPU) 10 be able to interrogate both a buffer 12 and a main store 14, while having the I/O 16 be capable of only interrogating the buffer 12.

CPU performance can usually be based on the average access times to storage. If most accesses are short and some are long, the average access time can normally be used as a reasonable measure of performance. However, I/O is normally time-dependent and the worst-case access times must be used in computing the maximum load the system can handle. In the case of I/O it does little good to have a storage which has an average access time of 500 nanoseconds, but has one out of every thousand references which require access time of 100 microseconds.

To solve this problem main storage is divided into two parts. In one part 12 data that can be rapidly accessed, or type A data, is maintained while in the other part 14 data which requires longer access times, or type B data, is stored. The CPU 10 can access either buffer storage unit 12 or main store 14, while I/O may only access the first part of storage 12 containing only type A data. If type B data is requested by I/O, the data must first be transferred from the second part 14 of storage to the first part 12 of storage to complete the request.

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